The invention relates to a multi-port bridge for a local area network. More particularly, the invention relates to a memory controller in a multi-port bridge for a local area network.
Nodes of a local area network (LAN) are typically interconnected by a shared transmission medium. The amount of data traffic that the shared transmission medium can accommodate, however, is limited. For example, only one node at a time can successfully transmit data to another node over the shared transmission medium. If two or more nodes simultaneously attempt to transmit data, a data collision occurs, which tends to corrupt the data being transmitted. Thus, nodes that share a transmission medium are considered to be in a same collision domain.
A multi-port bridge allows simultaneous communication between nodes of the LAN by segmenting the LAN into multiple collision domains (also referred to as network segments), each segment having a corresponding transmission medium. FIG. 1 illustrates a conventional local area network (LAN) including a multi-port bridge 20. The multi-port bridge 20 in this example has eight ports A-H, though the number of ports can vary. Each port A-H is connected to a segment 21-28 of the LAN. Each segment 21-28 typically includes one or more nodes 29-44, such as a workstation, a personal computer, a data terminal, a file server, a printer, a facsimile, a scanner or other conventional digital device. Each of the nodes 29-44 has an associated node address which uniquely identifies the node. The nodes 29-44 are configured to send data, one to another.
When the LAN operates according to Ethernet standards, such as the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard, data is communicated in the form of discrete packets. FIG. 2 illustrates a conventional IEEE 802.3 data packet 50. The data packet 50 includes an eight byte long pre-amble 51 which is generally utilized for synchronizing a receiver to the data packet 50. The preamble includes seven bytes of preamble and one byte of start-of-frame. Following the pre-amble 51, the data packet 50 includes a six byte long destination address 52, which is the node address of a node which is an intended recipient for the data packet 50. Next, the data packet 50 includes a six byte long source address 53, which is the node address of a node which originated the data packet 50. Following the source address 53 is a two-byte length field 54. Following the length field 54 is a data field 55. The data field 55 can be up to 1500 bytes long. Finally, the data packet 50 includes a four-byte frame check field 56 which allows a recipient of the data packet 50 to determine whether an error has occurred during transmission of the data packet 50.
When a node (source node) sends data to another node (destination node) located on its same segment of the LAN (intra-segment communication), the data is communicated directly between the nodes without intervention by the multi-port bridge 20 and is known as an intra-segment packet. Therefore, when the multi-port bridge 20 receives an intra-segment packet, the multi-port bridge 20 does not bridge the packet (the packet is filtered). When a node (source node) sends a data packet to another node (destination node) located on a different segment (inter-segment communication) the multi-port bridge 20 appropriately forwards the data packet to the destination node.
Memory is required in the multi-port bridge 20 for storing packets that are forwarded by the multi-port bridge 20. Therefore, what is needed is improved technique for controlling such memory.
The invention is a memory controller in a multi-port bridge for a local area network. The multi-port bridge includes a switch engine, a memory and a plurality of ports, all of which are interconnected by a high speed communication bus. The memory includes look-up tables utilized for appropriately directing data packets among the ports, packet buffers utilized for temporarily storing packets and mailboxes for providing an interface between the switch engine and an external processor. The switch engine includes the memory controller, a bus controller and a look-up controller, each preferably including a finite state machine.
The memory controller according to the present invention provides an interface between the memory and the communication bus by including a command decoder for decoding bus commands received from the communication bus. For example, the command decoder provides a response to memory read and write bus commands. In addition, the memory controller includes a memory control finite state machine for controlling operation of the memory controller according to the bus commands received from the command decoder. The memory controller also includes logic and address registers for providing appropriate row and column addresses to the memory device according to a current state of the memory control finite state machine. Because the memory control finite state machine controls operation of the memory controller, memory read and write operations are performed with a minimum of delay, thereby increasing the throughput capacity of the multi-port bridge.
The bus controller controls access to the communication bus by collecting requests and granting the requests according to an appropriate priority. The look-up controller determines to which port each packet is to be directed based upon the destination node address for the packet. The high speed communication bus includes single bit signal lines dedicated to communicating control commands, signal lines dedicated to communicating data, and several signal lines having special purposes. For example, two signal lines are preferably dedicated to initiating access to the bus, each having a respective priority, another signal line is dedicated to jam requests (for applying backpressure), still another signal line is dedicated to the memory controller and yet another signal line is dedicated to providing a bus clock signal.
Each port includes a port controller, a MAC transceiver, a receive finite state machine, a transmit finite state machine, a receive buffer, a transmit buffer and a memory pointer buffer. Packets received from a LAN segment by the transceiver are directed to the communication bus through the receive buffer, while packets to be transmitted over the LAN segment are directed to the transceiver through the transmit buffer. The memory pointer buffer stores memory pointers in a queue for transmission by the port, one memory pointer for each data packet being stored in the packet buffers of the memory.
A data packet originating from a node (source node) in a segment of the LAN is received by the receive buffer of a corresponding one of the ports (source port) of the multi-port bridge. As the packet is still being received, the look-up tables are utilized to determine which is the appropriate destination port for the packet based upon the destination address.
The communication bus is monitored by each port. The look-up controller indicates which are the destination ports for the packet via the communication bus. If the source port and the destination port are the same, this indicates that the source and destination nodes are on the same segment of the LAN (intra-segment communication) and the packet is filtered. Otherwise, if the port identified as the destination port is not currently busy transmitting or receiving another packet, the destination port configures itself to receive the packet directly from the source port (cut-through).
However, if the memory pointer buffer is nearly full, the port controller of the destination port applies a jam request signal to the communication bus. The source port receives the jam request and, in response, discards the incoming packet and also sends a jam signal over its associated segment. The jam signal causes the node (source node) which is the source of the packet to discontinue sending the packet and attempt to resend the packet after a waiting period.
Assuming the memory pointer buffer for the destination port is not nearly full (no jam request is made), the packet is loaded from the receive buffer of the source port into the packet buffers of the memory starting at the memory address identified in the memory pointer. Writing of the packet into the packet buffers preferably occurs as the remainder of the packet is still being received into the receive buffer of the source port. For this reason, the receive buffer for each port need not be capable of storing the entire data packet. In addition, if the destination port is configured for cut-through, the destination port receives the packet into its transmit buffer directly from the communication bus simultaneously with the write cycles for loading of the packet into the packet buffers. During such a cut-through operation, the packet is received into a transmit buffer of the destination port for immediate transmission to the LAN segment associated with the destination port.
Once the entire packet has been loaded into the packet buffers, the memory pointer is placed on the data lines of the communication bus. Each destination port stores the memory pointer in its memory pointer buffer. Thus, the packet is queued for transmission by the destination port. Then, when the destination port is no longer busy, the destination port retrieves the packet from the packet buffers.
While the destination port is receiving the packet into its transmit buffer from the packet buffers or directly from the source port, the destination port begins transmitting the packet to the network segment associated with the destination port. For this reason, the transmit buffer for each port need not be capable of storing an entire data packet. The destination node for the packet then begins to receive the packet from the network segment.
The memory controller according to the present invention, therefore, plays a central role in operation of the multi-port bridge by providing rapid memory access and by requiring only a minimum of activity on the communication bus for initiating memory read and write cycles. Accordingly, the multi-port bridge has a high packet handling capacity.